e-Shuttle Prototyping Achievement
Accumulated Number of e-Shuttle Implemented Projects for Academic Users
VDEC Paper List
2009
| Author(s) | Title | Journal in which paper was appeared |
| B. Devlin, M.G. Jeong, T. Nakura, M. Ikeda, and K. Asada | "647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA" | IEEE European Solid-State Circuits Conference(ESSCIRC), Sep. 2009 |
| B. Devlin, T. Nakura, M. Ikeda, and K. Asada | "Throughput optimization by pipeline alignment of a Self Synchronous FPGA" | IEEE International Conference on Field-Programmable Technology(ICFPT), Dec. 2009 |
| Islam, Tsuchiya, Kobayashi, Onodera, | "Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability" | TAU Workshop 2010 (2010/03) |
| Onodera, Terada, | "Characterization of WID Delay Variability Using RO-array Test Structures" | Proceedings 2009 8th IEEE International Conference on ASIC (2009/10) |
| Onodera, Terada | "Characterization of WID Delay Variability Using RO-array Test Structures" | 3rd IEEE International Workshop on Design for Manufacturability & Yield (2009/07) |
| Onodera | "Dependable VLSI Platform Using Robust Fabrics" | International Workshop on Emerging Circuits and Systems (2009/07) |
| Shota ISHIHARA, Xhengfan XIA, Masanori HARIYAMA, Michitaka KAMEYAMA |
"Architectureof a Low-Power FPGA Based Self-Adaptive Voltage Control" | IEICE Technicla Report, 2010-01. |
2008
| Author(s) | Title | Journal in which paper was appeared |
| M. Ikeda | "Delay Variation Measurements on DCVSL Using Logic Tester" | University of Tokyo - UC Santa Barbara Joint Workshop, Sept. 2008. |
| M. Ikeda | "Self-synchronous architecture for margin aware operations against PVT variations" | Shanghai Jiao Tong University - University of Tokyo Joint Symposium on Electronics, Information Technology, and Electrical Engineering, D-2, Oct. 2008. |
| M. Ikeda | "Self-Synchronous Architecture for Power Optimal Operations against PVT Variations" | the 8th Taiwan-Japan Microelectronics Symposium 2008, 4-6, Dec. 2008. |
| MyeongGyu Jeong, Makoto Ikeda, Kunihiro Asada, |
"Dynamic Circuit Design for Selftimed Fine-grained Pipeline Architecture" | IEICE General Conference, C-12-11, Mar. 2009. |
| D.Nakamura, H. Yoshida, S.Komatsu, M.Sasaki, M.Ikeda K.Asada, |
"Implementation and Chip Size Evaluation of an Realtime Onchip Monitoring System for Reliability of LSI" | IEICE General Conference, C-12-19, Mar. 2009.(in Japanese) |