| Items |
Descriptions |
| Electron Beam Lithography System |
Equipment that forms patterns of a semiconductor device to photo resist film on a wafer by using electron beam direct writing method instead of the existing optical lithography technology.
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| Electron Beam Direct Writing |
Lithography technology in which electron beams of several keV to 100 keV are used to "Expose" resist film on a wafer. The patterns of the elements of a semiconductor device are formed with by exposing resist film to a required patterns by scanning the electron beam.
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| MPW（Multi Project Wafer) method |
Method by which several different devices are manufactured on the same wafer for research and development by preparing masks on which several groups of devices or patterns are formed.
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| CLI |
LSI design tools developed by FUJITSU Semiconductor Limited.
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| Design Rule Check |
Tools(programs) that confirm whether patterns of each layer used when designed device is manufactured violates design rules
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| Process Monitor Check |
Elements to evaluate the characteristics of devices in a semiconductor die. They are for example, resistor, capacitor, interconnect, and they are mounted in open area of a wafer, for example, on the scribe line between die.
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| frame |
An area where the circuit of a die is mounted at a semiconductor desin. The origin of a frame to place elements and the pads are installed.
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| tape out(TO) |
This means the completion of circuit design of a semiconductor. It is called because the manufacturing of masks used is begun from this point.
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| Process Design Kit |
A set of tools(softwares) required for semiconductor circuit design.
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| run |
A trial production lot for prototyping service of semiconductor device. The lot is composed of some wafers and on each wafer, the die of several protyping service users will be manufactured.
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| hot run |
The lot of a run which is progressed in the manufacturing process with higher TAT than a usual run.
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| super hot run |
The lot of a run which is progressed in the manufacturing process with higher TAT than a usualhot run.
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| TAT(Turn Around Time) |
It is a scale that indicates progress rate of manufacturing steps. In the manufacturing process consisting of two or more steps, the progress rate is shown by the number of steps that can be progressed in a day. It is said that the higher the rate is, the faster the progress of manufacturing is. (Use in our company)→Days from the start of manufacturing to the product completion（Universal use）
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| wafer |
It is a disk made from silicon single crystal is used as a substrate on which semiconductor devices are manufactured. The wafer of 300mm in the diameter is mainly used now.
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| block |
One region of semiconductor device whose size is a half or 1/4 of single-die(chip) usually offered by our shuttle service.
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| big die |
One region of semiconductor device whose size is two or more of single-die(chip) combined in lateral and/or vertical direction(s).
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| die(chip) |
Semiconductor element consisting of a circuit with a certain function. It is equipped with terminals to connect with other device and mounted in a package to protect the device from the external environment, and is used as a general semiconductor device.
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| dicing |
To divide several square chips (die) manufactured on a round wafer to be each chip (die).
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| electron beam |
State where electrons gather and flow in the straight line.
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| electron beam |
Device that emits electrons from solid surface into Vacuum by using heat or electric field
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| filament |
A part of electron gun where electrons are actually emitted
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| deflection |
To control the travelling direction of the electron beam by applying the magnetic field or the electric field.
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| aperture |
Device that converges electron beam to be thinner in electron beam lithography system
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| Variable Shaped Beam(VSB) |
In electron beam lithography system, a method to mold the cross-sectional shape of electron beam into the shape of logical product of two comparatively big rectangular apertures by passing through them.
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| Character Projection Method/Cell Projection Method(CP Method) |
It is the method in which the shapes often used by the LSI manufacturing are registered as apertures of the electron beam lithography system in the system, and they are used if necessary, to reform the electron beam to the required shape and to expose the shape on a wafer.
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| (photo)resist |
Organic compound used in the lithography process of semiconductor manufacturing whose characteristics would be changed with light or electron beam. The required shape is formed on the surface of the wafer by using this change.
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| block mask/stencil mask |
The bolcks shaped according to the specified devices. They are used by the Character Projection Method or Cell Projection Method.
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| Micro Electro Mechanical System(MEMS) |
The technology by which electronic devices and minute moving mechanism are manufactured on the same wafer by using semiconductor manufacturing technology, or the manufactured unit.
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| standard cell |
A custom LSI which is designed by a customer with combining function blocks that a semiconductor manufacturer offers and manufactured by the manufacturer. Or, These function blocks might be called so.
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| Design For Manufacturing(DFM) |
It is said "Design for Manufacturing, and the technology realizes the design to be easily manufactured with highe yield from the design stage to shorten the development period and to reduce the manufacturing cost.
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| In-situ cleaning method |
In the electron beam lithography system, as for impurities (carbon from the photo resist) that adhere in the vacuum system, the techniques for introducing the oxygen plasma making them react chemical, and keeping the cleanliness of the device inner surface by without breaking the vacuum in the device, without breaking the vacuum in the device,.
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| Self-cleaning method |
Cleaning method of using a small amount of ozone for replacement of oxygen plasma used by cleaning technique in situ
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| TLFD(Target Lithography Friendly Design) method |
The method to generatea basic pattern data for EBDW conforming to the final pattern finally formed on a wafer.
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| CoO(Cost of Ownership) |
It is an index that shows the productivity of the process and the manufacturing equipment in LSI mass production line. When the investment efficiency of LSI line or the manufacturing equipment is evaluated, it is used as the criteria.
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| nanoimprint technology |
The technology to form the shape of the patterns on the mold on the resin film of the substrate by using the metal mold where the asperities of tens to hundreds nm are graved. This technology is inferior in the ultra precision processing but superior in the process throughput to the lithography technology.
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| EUV (Extreme Ultraviolet) Lithography |
One type of reduced projection lithography using extreme-ultraviolet light of wavelength of 13nm to 14nm. Extreme-Ultra Violet (EUV) light is a light of a very short wavelength range in the soft X-ray.
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| hybrid lithography |
The technology in which, by using the characteristics that a resist film for EBDW is also exposed by KrF(krypton fluoride) laser light, the larger areas are exposed by KrF laser and smaller areas by EBDW.
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| via |
Holes of the line width which are opend in the insulator films between upper and lower interconnect layers for electrically connecting those interconnect layers.
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| Multi-beam EBDW |
To scan several electron beams at the same time in parallel by setting the several sources of the electron beam to achieve a practicable drawing speed in the electron beam exposure system.
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| multi column cell |
Technology to improve the throughput of the electron beam lithography system by providing plural "Column cells" with functions such as electron gun etc. equivalent to an electron optical system of single electron beam lithography system, and drawing two or more areas on one substrate (a wafer etc.) simultaneously in parallel.
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| interconnect layer |
Layer of wiring that connect circuits and devices
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| hole layer |
Layer where holes to connect multilayer and to connect devices such as transistor etc. with interconnect are formed.
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| bulk layer |
Layers such as active layer where function areas are made by isolating transistors and gate layer where gate terminals of transistors are formed.
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| design for e-beam (DFEB) technology |
Technology to improve the throughput of the electron beam (EB) lithography system by taking advantage of the design and software technologies. By combining character projection (CP) EB technology with various new design and software technologies, DFEB could minimize the number of shots required for drawing the circuit and improve the throughput of the EB lithography system.
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| trial production |
Before the mass-production of a product, to study the characteristics and productivity of the product, small amount of the product is produced.
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| ES(engineering sample) |
Prototyped product to evaluate the electrical characteristics of the product. The quality of the product is NOT guaranteed generally.
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